1. Technical Field
The present invention relates in general to data processing system and, in particular, to methods, systems and program products for interrupt handling in a data processing system. Still more particularly, the present invention relates to methods, systems, and program products for emulating an interrupt architecture in a data processing system.
2. Description of the Related Art
In computer systems, interrupts are often utilized to alert a processor to the occurrence of an event that requires special handling. Interrupts may be utilized, for example, to request service from a recipient processor, report an error condition or receipt of data, or simply communicate information between devices.
In conventional multiprocessor (MP) computer systems, interrupts have been handled in a variety of ways, utilizing hardware and/or software mechanisms. Conventional MP computer systems may employ a global interrupt controller that selects a processor to service an external or inter-processor interrupt based, for example, upon the priority of the interrupt and the priority of the process, if any, being executed by each processor. In order to facilitate efficient handling of interrupt-related communication, the global interrupt controller and the processors communicate interrupt requests, end-of-interrupt (EOI) messages, processor priorities and other interrupt-related information utilizing specific hardware registers and/or predefined memory address offsets.
One difficulty with implementing an interrupt scheme in a data processing system is that the various hardware and software components that a designer may desire to include within the data processing system may not all be compliant with a single interrupt standard, such as the non-proprietary OpenPIC (Open Programmable Interrupt Controller) architecture or the proprietary I/O APIC (Input/Output Advanced Programmable Interrupt Controller) architecture developed by Intel Corporation of Santa Clara, Calif. The inconsistencies between the various interrupt architectures in interrupt communication, bit ordering, interrupt priority designations, etc. can create incompatibilities with both interrupt hardware and operating system software.
The present invention appreciates that, despite such apparent incompatibilities, it would be desirable to develop a data processing system from hardware and software components implementing heterogeneous interrupt architectures.